1. Field of the Invention
The present invention generally relates to non-volatile memory chips and more particularly to an architecture for a three-dimensional, direct-write non-volatile random access memory (NVRAM).
2. Background Description
Non-volatile floating gate memory cells, such as in a non-volatile random access memory (NVRAM) are well known in the industry. In such NVRAM cells, the cell's conductive state is determined by the charge state of the cell's floating gate. The floating gate is an electrically isolated gate of a field effect transistor (FET) stacked in a two device NAND-like structure. Charge is forced onto or removed from the floating gate through a thin insulator layer that, normally (during a read operation), isolates the gate electrically from other adjoining conductive layers. Typically, a negatively charged floating gate is representative of a binary one state, while an uncharged floating gate is representative of a binary zero state.
The other device in the NAND-like structure is connected to a wordline and a bitline and provides for selective cell read and write selection. In typical state of the art designs, adjacent cells are connected to a common bitline. The wordlines of these adjacent cells must be uniquely addressable and physically distinct.
For writing cells, a control gate (or program gate) is capacitively coupled to floating gates of cells in a portion of an array. A program voltage placed on a control gate biases the floating gate of cell connected to the control gate sufficiently to change the charge on the cell's floating gate, i.e. to write selected cells.
Normally, to write data into a prior art memory cell, the cell must first be erased and then written. Each of these operations may require one or more machine cycles, e.g., 10 milliseconds, and each requires a significantly higher external voltage supply, such as 15-20 volts. Special decoder circuits are used to provide these higher than normal voltages to the cells.
It is a normal design goal to minimize cell size, thereby maximizing cell density. However, memory designers have not achieved a state of the art unit cell that is smaller than 6-8 squares, where a square is the smallest unit design area for a given technology, e.g., 0.2 .mu.m.times.0.2 .mu.m. Any device fabrication technique improvements that produce a denser memory array and reduce chip power requirements.
Thus, there is a need for smaller, denser NVRAM array and NVRAM chips.